Synopsys IC Validator, Running on AMD EPYC Processor Powered Azure Virtual Machines, Verifies AMD Radeon Pro VII GPU Design in Under Nine Hours

MOUNTAIN VIEW, Calif., Aug. 20, 2020

Highlights:

• Cloud-optimized IC Validator scales physical verification across approximately 4,000 AMD EPYC^™ cores to deliver overnight full-chip DRC runtime
• Unique elastic CPU management enabled optimal use of compute resources
• Reference setup enables users to get started with IC Validator on Microsoft Azure cloud

Synopsys, Inc. (Nasdaq: SNPS) today announced that its IC Validator physical verification solution running on Microsoft Azure completed a verification run of the AMD Radeon™ Pro VII GPU, which includes more than 13 billion transistors, in less than nine hours. The collaboration was powered by Azure HBv2 virtual machines, using the 2^nd Generation AMD EPYC^™ processors.

IC Validator utilized unique elastic CPU management technology to realize up to 40 percent savings in compute resources, achieving lower cost of ownership on cloud and ensuring resource availability for other critical jobs during tapeout.

"At AMD, on-time execution of our products is critical to supporting our goal of providing leadership products in high-performance computing," said Mydung Pham, corporate vice president, Silicon Design Engineering, AMD. "The AMD EPYC processor-based Azure HBv2 virtual machines are a great fit for high-performance workloads, and we are excited to see Synopsys use them to power its IC Validator solution, helping customers validate hardware and chip design in a short timeframe."

"Increasing design sizes and complexity in silicon design is driving the industry to think about the compute infrastructure differently," said Mujtaba Hamid, head of product, Silicon, Electronics and Gaming, at Microsoft Azure. "Taping out chips with exponentially growing transistor counts, on schedule, remains an imperative for the industry. Azure enables silicon design teams to do so in a secure and cost-effective manner through an EDA-optimized, scalable cloud infrastructure."

IC Validator is a comprehensive and highly scalable physical verification solution, that includes DRC, LVS, programmable electrical rule checks (PERC), dummy metal fill, and design-for-manufacturability (DFM) enhancement capabilities. IC Validator is architected for high performance and scalability, which maximizes utilization of mainstream hardware, using smart memory-aware load scheduling and balancing technologies. It uses both multi-threading and distributed processing across multiple machines to provide scalability benefits that extend to thousands of CPUs.